1. Field of the Invention
The present invention relates to a semiconductor device which comprises semiconductor chips mounted on a board, and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device of a conventional BGA (Ball Grid Array) structure is known, for example, from a structure described in JP2001-044229A (Document 1). This BGA-structured semiconductor device comprises a wiring board. On one surface, the wiring board is formed with a predetermined circuit and is also mounted with a semiconductor chip formed with a plurality of electrode pads. On the other surface of the wiring board, in turn, a plurality of external terminals are arranged in a lattice form, corresponding to the electrode pads on the semiconductor chip. Then, the electrode pads on the semiconductor chip are electrically connected with the external terminals corresponding to the electrode pads through a wiring pattern on the wiring board, and the like. On the one surface of the wiring board, a sealant is formed so as to cover at least the semiconductor chip and electric connections between the semiconductor chip and the wiring board.
Such semiconductor devices that have a conventional BGA structure are manufactured, for example, using a MAP (Mold Array Process) method, by collectively sealing a plurality of semiconductor chips disposed on a wiring board.
A semiconductor device that has a conventional BGA structure comprises a semiconductor chip securely adhered on a wiring board using DAF (Die Attach Film), an adhesive or the like. Then, the semiconductor device undergoes a reflow process, where balls which serve as external terminals of the wiring board are melted, and is bonded to a mounting board so that the semiconductor device is mounted on the mounting board. A semiconductor device is assembled by securely adhering a semiconductor chip, a wiring board and the like which are made of a plurality of types of materials each having different coefficients of thermal expansion.
Accordingly, the entire semiconductor device suffers from warpage due to a rise in temperature of the semiconductor device during a reflow process. As a result, stress is applied to external terminals bonded on a mounting board. This stress causes the external terminals to break, to peel off from the mounting board, and other phenomena. For this reason, the electrically connection in the connected state of the semiconductor device and the mounting board is damaged, possibly resulting in degraded reliability of the semiconductor device.
As an action taken to address the foregoing problem, JP11-087414A (Document 2), for example, proposes a structure which includes an elastic member (elastomer) sandwiched between a semiconductor chip and a wiring board in order to alleviate stress which occurs between the semiconductor chip and the wiring board.
JP10-189820A (Document 3), in turn, discloses a structure for preventing a package of a semiconductor device from cracking. In this structure, a semiconductor chip is mounted, by way of a die bond film, on a board which has a bonding sheet formed with a wiring pattern and throughholes, such that a gap is formed between the die bond film and the bonding sheet to communicate with the through holes.
Then, the present inventors have recognized the following problems.
The elastomer, which is used as an elastic material in the configuration of aforementioned Document 2, is a very expensive material, and therefore causes an increase in the manufacturing cost of semiconductor devices.
On the other hand, in the configuration described in aforementioned Document 3, since a semiconductor chip is directly secured on a board, stress will occur due to the difference in the coefficients of thermal expansion between the semiconductor chip and the board. For this reason, reliability of the semiconductor device can undergo degradation because solder balls, which serve as external terminals, are damaged in a reflow process.
Also, in the configuration described in Document 3, a die bond film is applied on the entire back surface of a semiconductor chip. Thus, if a void occurs between the die bond film and the semiconductor chip, the package is likely to suffer from cracking during the reflow process for solder balls. Further, due to the employment of the die bond film, this configuration can cause an increase in the manufacturing cost of the semiconductor device.
Moreover, in the configuration described in Document 3, a semiconductor chip is bonded only to wiring metal laminated on a bonding sheet which forms part of the board. Therefore, in this configuration, the wiring metal can be broken because stress intensively acts on the wiring metal which is caused by the effect of a thermal history in the reflow process or by the effect of thermal cycling.